As is well known, arrays of static random access memory (SRAM) cells can be used to maintain logic states corresponding to various associated data values. Individual SRAM cells of such arrays may be implemented, for example, using cross-coupled logic gates. It is generally desirable for SRAM cells to hold their stored logic states despite possible changes in voltage, temperature, or other operating conditions. It is also desirable for SRAM cells to permit changes in their logic states in response to write operations. Unfortunately, existing SRAM cell designs often fail to provide high degrees of both stability and writeability.
Certain SRAM cell designs can suffer stability problems. For example, the logic states of some SRAM cells of an array may be disturbed when write operations are performed on other SRAM cells in the array. This can be particularly troublesome for SRAM cells having bidirectional read/write ports that are enabled by word lines shared by other SRAM cells. The possibility of such disturbances can limit the various ways in which such SRAM cells may be operated.
In this regard, it may be necessary to avoid performing column multiplexing operations or partial-word write operations on such SRAM cells. However, this can limit the area efficiency, speed efficiency, and increase the control logic complexity associated with such SRAM cells. Such bidirectional-ported SRAM cells may alternatively be operated in a read-modify-write manner in which the complete content of a row of SRAM cells is read out, and then the read data and new write data are combined and written back into the row. Such an approach can significantly reduce the operating frequency of SRAM cells (for example, by approximately 50%), requires additional expensive control circuitry, can limit the area efficiency, and complicates data verification.
In order to reduce the possibility of such disturbances, SRAM cells may be implemented with separate unidirectional ports for reading and writing operations. For example, a plurality of write ports may be provided for writing different logic states into SRAM cells in the same row or column. Unfortunately, SRAM cells using multiple write ports may not always be compatible with other approaches that are used to improve the writeability of SRAM cells. Moreover, as SRAM operating voltages are reduced, variations in operating conditions and SRAM components can more easily impact the operation of SRAM cells which can have a correspondingly greater effect on stability and writeability.